Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and/or receive signals external to the chip. One popular type of interconnection are copper interconnections (lines) that coupled to individual devices, including other interconnections (lines) by interconnections through vias.
A typical method of forming an interconnection, particularly a copper interconnection, is a damascene process. A typical damascene process involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection. The via and trench are then lined with a barrier layer of a refractory material, such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or their combinations. The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material that will subsequently be introduced in the via and trench into the dielectric. Next, a suitable seed material is deposited on the wall or walls of the via and trench. Suitable seed materials for the deposition of copper interconnection material include copper (Cu), nickel (Ni), and cobalt (Co). Interconnection material, such as copper, is then deposited by electroplating or physical deposition in a sufficient amount to fill the via and trench and complete the interconnection structure. Once introduced, the interconnection structure may be planarized and a dielectric material (including an interlayer dielectric material) introduced over the interconnection structure to suitably isolate the structure.
Advancements in integrated circuit processing have dictated that a line width of an interconnection structure and therefore its correspondence via and trench openings be reduced. As line widths are reduced to 60 nanometers or less, aspect ratios, measured as a thickness of the dielectric relative to a line width of the opening of the via/trench, can be on the order of four to one or five to one (e.g., assuming a dielectric thickness on the order of 200 nanometers). When the interconnect openings are lined with a barrier layer and a seed material, the opening left for plating copper is very narrow making it increasingly difficult to electroplate copper into the openings (e.g., electroplating copper into openings having aspect ratios that may approach 20 to one or greater). If the thickness of the barrier layer and/or seed material is reduced, the electroplating of copper may be compromised. If the thickness of the barrier layer and/or seed material are too thick, the combined thickness can “pinch-off” the interconnection opening leading to voids even before plating. Thus, it remains a challenge to achieve an optimum barrier layer and seed material thickness for a continuous coverage on interconnection opening side walls and a wide enough opening of features for electroplating.